HD64F3437TF16 Datasheet, PDF (574/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from software standby mode by an external interrupt. During the
selected time, the clock oscillator runs but the CPU and on-chip supporting modules remain in
standby. Set bits STS2 to STS0 according to the clock frequency to obtain a settling time of at
least 8 ms. See table 22.3.
• ZTAT and Mask ROM Versions
Bit 6: STS2
0
1
Bit 5: STS1
0
1
0
1
Bit 4: STS0
0
1
0
1
—
—
Description
Settling time = 8,192 states
Settling time = 16,384 states
Settling time = 32,768 states
Settling time = 65,536 states
Settling time = 131,072 states
Unused
(Initial value)
• F-ZTAT Version
Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description
0
0
0
Settling time = 8,192 states
(Initial value)
1
Settling time = 16,384 states
1
0
Settling time = 32,768 states
1
Settling time = 65,536 states
1
0
0
Settling time = 131,072 states
1
Settling time = 1,024 states
1
—
Unused
Note: When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted.
If a period exceeding øp/1,024 (e.g. øp/2,048) is specified when selecting the 8-bit timer,
PWM timer, or watchdog timer clock, the counter in the timer will not count up normally
when 1,024 states is specified for the settling time. To avoid this problem, set the STS value
just before the transition to software standby mode (before executing the SLEEP
instruction), and re-set the value of STS2 to STS0 to a value from 000 to 100 directly after
software standby mode is cleared by an interrupt.
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