HD64F3437TF16 Datasheet, PDF (298/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Figure 12.8 shows an example of SCI receive operation in asynchronous mode.
Start
1 bit
Data
Parity Stop Start
bit bit bit
Parity Stop
Data bit bit
1
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 0 Idle state
(mark)
RDRF
FER
1 frame
RXI
request
RXI interrupt handler
reads data in RDR and
clears RDRF to 0
Framing error,
ERI request
Figure 12.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID.
A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the
receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending
cycles from data-sending cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1.
After receiving data with the multiprocessor bit set to 1, the receiving processor with an ID
matching the received data continues to receive further incoming data. Multiple processors can
send and receive data in this way.
Four formats are available. Parity-bit settings are ignored when a multiprocessor format is
selected. For details see table 12.9.
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