HD64F3437TF16 Datasheet, PDF (286/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

12.2.9 Serial/Timer Control Register (STCR)
Bit
7
6
5
4
IICS
IICD IICX
IICE
Initial value
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
3
STAC
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
0
ICKS0
0
R/W
STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the
TCNT clock source in the 8-bit timers. STCR is initialized to H'00 by a reset.
Bits 7 to 4—I²C Control (IICS, IICD, IICX, IICE): These bits control operation of the I²C bus
interface. For details, refer to section 13, I²C Bus Interface.
Bit 3—Slave Input Switch (STAC): Controls the input pin of the host interface. For details,
section 14, Host Interface.
Bit 2—Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication
function on channels SCI0 and SCI1.
Bit 2: MPE
0
1
Description
The multiprocessor communication function is disabled, regardless of the
setting of the MP bit in SMR.
(Initial value)
The multiprocessor communication function is enabled. The multi-processor
format can be selected by setting the MP bit in SMR to 1.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits select the
clock input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit
Timers.
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