HD64F3437TF16 Datasheet, PDF (744/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents when the RAME bit in SYSCR is set to 1, drive the RES signal low
10 system clock cycles before the STBY signal goes low, as shown below. RES must remain
low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
STBY
t₁ ≥ 10 t_cyc
t₂ ≥ 0 ns
RES
(2) When the RAME bit in SYSCR is cleared to 0 or when it is not necessary to retain RAM
contents, RES does not have to be driven low as in (1).
Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
RES
t ≥ 100 ns
t_OSC
715