HD64F3437TF16 Datasheet, PDF (321/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

13.2.5 I²C Bus Status Register (ICSR)
Bit
Initial value
Read/Write
7
BBSY
0
R/W
6
IRIC
0
R/(W)*
5
SCP
1
W
4
3
2
1
0
—
AL
AAS ADZ ACKB
1
0
0
0
0
— R/(W)* R/(W)* R/(W)* R/W
Note: * Only 0 can be written, to clear the flag.
ICSR is an 8-bit readable/writable register with flags that indicate the status of the I²C bus
interface. It is also used for issuing start and stop conditions, and recognizing and controlling
acknowledge data.
ICSR is initialized to H'30 by a reset and in hardware standby mode.
Bit 7—Bus Busy (BBSY): This bit can be read to check whether the I²C bus (SCL and SDA) is
busy or free. In master mode this bit is also used in issuing start and stop conditions.
A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting
BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,
clearing BBSY to 0.
To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, use a MOV instruction to
write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode.
Bit 7: BBSY
0
1
Description
Bus is free
This bit is cleared when a stop condition is detected.
Bus is busy
This bit is set when a start condition is detected.
(Initial value)
292