HD64F3437TF16 Datasheet, PDF (119/752 Pages) Hitachi Semiconductor – 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device.

6.1.2 Wait-State Control Register (WSCR)
WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals
supplied to the supporting modules. It also controls wait state controller wait settings, RAM area
setting for dual-power-supply flash memory, and selection/non-selection of single-power-supply
flash memory control registers.
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
Initial value
Read/Write
7
RAMS^*1
0
R/W
6
RAM0^*1
0
R/W
5
4
CKDBL FLSHE^*2
0
0
R/W
R/W
3
WMS1
1
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
0
WC0
0
R/W
Notes: *1 These bits are valid only in the H8/3437F and H8/3434F (dual-power-supply on-chip
flash memory versions).
*2 This bit is valid only in the H8/3437SF (S-mask model, single-power-supply on-chip
flash memory version).
Bit 7—RAM Select (RAMS)
Bit 6—RAM Area Select (RAM0)
Bits 7 and 6 select a RAM area for emulation of dual-power-supply flash memory updates. For
details, see the flash memory description in section 19, 20, ROM.
Bit 5—Clock Double (CKDBL): Controls the frequency division of clock signals supplied to
supporting modules.
Bit 5: CKDBL
0
1
Description
The undivided system clock (ø) is supplied as the clock (ø_P) for supporting
modules.
(Initial value)
The system clock (ø) is divided by two and supplied as the clock (ø_P) for
supporting modules.
Bit 4—Flash Memory Control Register Enable (FLSHE): Controls selection/non-selection of
single-power-supply flash memory control registers. For details, see the description of flash
memory in section 21, ROM. In models other than the H8/3437SF, this bit is reserved, but it can
be written and read; its initial value is 0.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0)
Bits 1 and 0—Wait Count 1 and 0 (WC1/0)
These bits control wait-state insertion. For details, see section 5, Wait-State Controller.
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