C8051F960-B-GM Datasheet, PDF (93/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte
Bit
7
6
5
4
3
2
1
0
Name
AD0LT[15:8]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC6
Bit Name
Function
7:0 AD0LT[15:8] ADC0 Less-Than High Byte.
Most Significant Byte of the 16-bit Less-Than window compare register.
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte
Bit
7
6
5
4
3
2
1
0
Name
AD0LT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xC5
Bit Name
Function
7:0 AD0LT[7:0] ADC0 Less-Than Low Byte.
Least Significant Byte of the 16-bit Less-Than window compare register.
Note: In 8-bit mode, this register should be set to 0x00.
5.6.1. Window Detector In Single-Ended Mode
Figure 5.5 shows two example window comparisons for right-justified data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.6 shows an example using left-justi-
fied data with the same comparison values.
Rev. 1.0
93