C8051F960-B-GM Datasheet, PDF (152/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 11.3. DMA0MINT: DMA0 Mid-Point Interrupt
Bit
Name
Type
Reset
7
6
5
4
3
2
1
0
CH6_MINT CH5_MINT CH4_MINT CH3_MINT CH2_MINT CH1_MINT CH0_MINT
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xD4
Bit
Name
Function
7
Unused
Read = 0b, Write = Don’t Care
6
CH6_MINT _{Channel 6 Mid-Point Interrupt Flag.}
0: Mid-Point interrupt has not occured on channel 6.
1: Mid-Point interrupt has not occured on channel 6.
5
CH5_MINT _{Channel 5 Mid-Point Interrupt Flag.}
0: Mid-Point interrupt has not occured on channel 5.
1: Mid-Point interrupt has not occured on channel 5.
4
CH4_MINT _{Channel 4 Mid-Point Interrupt Flag.}
0: Mid-Point interrupt has not occured on channel 4.
1: Mid-Point interrupt has not occured on channel 4.
3
CH3_MINT _{Channel 3 Mid-Point Interrupt Flag.}
0: Mid-Point interrupt has not occured on channel 3.
1: Mid-Point interrupt has not occured on channel 3.
2
CH2_MINT _{Channel 2 Mid-Point Interrupt Flag.}
0: Mid-Point interrupt has not occured on channel 2.
1: Mid-Point interrupt has not occured on channel 2.
1
CH1_MINT _{Channel 1 Mid-Point Interrupt Flag.}
0: Mid-Point interrupt has not occured on channel 1.
1: Mid-Point interrupt has not occured on channel 1.
0
CH0_MINT _{Channel 0 Mid-Point Interrupt Flag.}
0: Mid-Point interrupt has not occured on channel 0.
1: Mid-Point interrupt has not occured on channel 0.
Note: Mid-point Interrupt flag is set when the offset address DMA0NAOH/L equals to half of data transfer
size DMA0NSZH/L if the transfer size is an even number or half of data transfer size
DMA0NSZH/L plus one if the transfer size is an odd number. This flag must be cleared by software
or system reset.The mid-point interrupt is enabled by setting bit 6 of DMA0NCF with DMA0SEL configured
for the corresponding channel.
152
Rev. 1.0