C8051F960-B-GM Datasheet, PDF (189/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
14.5.2. AES Block Cipher Decryption using SFRs
 First Configure AES Module for AES Block Cipher
Reset AES module by writing 0x00 to AES0BCFG.
Configure the AES Module data flow for AES Block Cipher by writing 0x00 to the AES0DCFG sfr.
Write key size to bits 1 and 0 of the AES0BCFG.
Configure the AES core for decryption by setting bit 2 of AES0BCFG.
Enable the AES core by setting bit 3 of AES0BCFG.
 Repeat alternating write sequence 16 times
Write ciphertext byte to AES0BIN.
Write decryption key byte to AES0KIN.
 Write remaining decryption key bytes to AES0KIN for 192-bit and 256-bit decryption only.
 Wait on AES done interrupt or poll bit 5 of AES0BCFG.
 Read 16 plaintext bytes from the AES0YOUT sfr.
If decrypting multiple blocks, this process may be repeated. It is not necessary reconfigure the AES mod-
ule for each block.
Rev. 1.0
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