C8051F960-B-GM Datasheet, PDF (4/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
11.2.1. DMA0 Memory Access Arbitration ........................................................ 148
11.2.2. DMA0 Channel Arbitration .................................................................... 148
11.3. DMA0 Operation in Low Power Modes ......................................................... 148
11.4. Transfer Configuration................................................................................... 149
12. Cyclic Redundancy Check Unit (CRC0)............................................................. 160
12.1. 16-bit CRC Algorithm..................................................................................... 160
12.3. Preparing for a CRC Calculation ................................................................... 163
12.4. Performing a CRC Calculation ...................................................................... 163
12.5. Accessing the CRC0 Result .......................................................................... 163
12.6. CRC0 Bit Reverse Feature............................................................................ 167
13. DMA-Enabled Cyclic Redundancy Check Module (CRC1)............................... 168
13.1. Polynomial Specification................................................................................ 168
13.2. Endianness.................................................................................................... 169
13.3. CRC Seed Value ........................................................................................... 170
13.4. Inverting the Final Value................................................................................ 170
13.5. Flipping the Final Value ................................................................................. 170
13.6. Using CRC1 with SFR Access ...................................................................... 171
13.7. Using the CRC1 module with the DMA ......................................................... 171
14. Advanced Encryption Standard (AES) Peripheral ............................................ 175
14.1. Hardware Description .................................................................................... 176
14.1.1. AES Encryption/Decryption Core .......................................................... 177
14.1.2. Data SFRs............................................................................................. 177
14.1.3. Configuration sfrs .................................................................................. 178
14.1.4. Input Multiplexer.................................................................................... 178
14.1.5. Output Multiplexer ................................................................................. 178
14.1.6. Internal State Machine .......................................................................... 178
14.2. Key Inversion................................................................................................. 179
14.2.1. Key Inversion using DMA...................................................................... 180
14.2.2. Key Inversion using SFRs..................................................................... 181
14.2.3. Extended Key Output Byte Order.......................................................... 182
14.2.4. Using the DMA to unwrap the extended Key ........................................ 183
14.3. AES Block Cipher .......................................................................................... 184
14.4. AES Block Cipher Data Flow......................................................................... 185
14.4.1. AES Block Cipher Encryption using DMA ............................................. 186
14.4.2. AES Block Cipher Encryption using SFRs ............................................ 187
14.5. AES Block Cipher Decryption........................................................................ 188
14.5.1. AES Block Cipher Decryption using DMA............................................. 188
14.5.2. AES Block Cipher Decryption using SFRs............................................ 189
14.6. Block Cipher Modes ...................................................................................... 190
14.6.1. Cipher Block Chaining Mode................................................................. 190
14.6.2. CBC Encryption Initialization Vector Location....................................... 192
14.6.3. CBC Encryption using DMA .................................................................. 192
14.6.4. CBC Decryption .................................................................................... 195
14.6.5. Counter Mode ....................................................................................... 198
14.6.6. CTR Encryption using DMA .................................................................. 200
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Rev. 1.0