C8051F960-B-GM Datasheet, PDF (443/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 31.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing (See Figure 31.8 and Figure 31.9)
T_MCKH
SCK High Time
1 x T_SYSCLK
—
ns
T_MCKL
SCK Low Time
1 x T_SYSCLK
—
ns
T_MIS
MISO Valid to SCK Shift Edge
1 x T_SYSCLK + 20
—
ns
T_MIH
SCK Shift Edge to MISO Change
0
—
ns
Slave Mode Timing (See Figure 31.10 and Figure 31.11)
T_SE
NSS Falling to First SCK Edge
2 x T_SYSCLK
T_SD
Last SCK Edge to NSS Rising
2 x T_SYSCLK
T_SEZ
NSS Falling to MISO Valid
—
T_SDZ
NSS Rising to MISO High-Z
—
T_CKH
SCK High Time
5 x T_SYSCLK
T_CKL
SCK Low Time
5 x T_SYSCLK
T_SIS
MOSI Valid to SCK Sample Edge
2 x T_SYSCLK
T_SIH
SCK Sample Edge to MOSI Change
2 x T_SYSCLK
T_SOH
SCK Shift Edge to MISO Change
—
T_SLH
Last SCK Edge to MISO Change 
(CKPHA = 1 ONLY)
6 x T_SYSCLK
Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
—
ns
—
ns
4 x T_SYSCLK ns
4 x T_SYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x T_SYSCLK ns
8 x T_SYSCLK ns
Rev. 1.0
443