C8051F960-B-GM Datasheet, PDF (229/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
PC0INT0
0xFB
0x2 _{PC0 Interrupt 0}
PC0INT1
0xFC
0x2 PC0 Interrupt 1
PC0MD
0xD9
0x2 _{PC0 Mode}
PC0PCF
0xD7
0x2 _{PC0 Pull-up Configuration}
PC0STAT
0xC1
0x2 PC0 Status
PC0TH
0xE4
0x2 _{PC0 Threshold}
PCA0CN
0xD8 All Pages _{PCA0 Control}
PCA0CPH0
0xFC
0x0 PCA0 Capture 0 High
PCA0CPH1
0xEA
0x0 _{PCA0 Capture 1 High}
PCA0CPH2
0xEC
0x0 _{PCA0 Capture 2 High}
PCA0CPH3
0xEE
0x0 PCA0 Capture 3 High
PCA0CPH4
0xFE
0x0 _{PCA0 Capture 4 High}
PCA0CPH5
0xD3
0x0 _{PCA0 Capture 5 High}
PCA0CPL0
0xFB
0x0 PCA0 Capture 0 Low
PCA0CPL1
0xE9
0x0 _{PCA0 Capture 1 Low}
PCA0CPL2
0xEB
0x0 _{PCA0 Capture 2 Low}
PCA0CPL3
0xED
0x0 PCA0 Capture 3 Low
PCA0CPL4
0xFD
0x0 _{PCA0 Capture 4 Low}
PCA0CPL5
0xD2
0x0 _{PCA0 Capture 5 Low}
PCA0CPM0
0xDA
0x0 PCA0 Module 0 Mode Register
PCA0CPM1
0xDB
0x0 _{PCA0 Module 1 Mode Register}
PCA0CPM2
0xDC
0x0 PCA0 Module 2 Mode Register
PCA0CPM3
0xDD
0x0 _{PCA0 Module 3 Mode Register}
PCA0CPM4
0xDE
0x0 _{PCA0 Module 4 Mode Register}
PCA0CPM5
0xCE
0x0 PCA0 Module 5 Mode Register
PCA0H
0x0 _{PCA0 Counter High}
PCA0L
0xF9
0x0 _{PCA0 Counter Low}
PCA0MD
0xD9
0x0 PCA0 Mode
PCA0PWM
0xDF
0x0 _{PCA0 PWM Configuration}
PCLKACT
0xF5
0xF _{Peripheral Clock Enable Active Mode}
PCLKEN
0xFE
0xF Peripheral Clock Enables (LP Idle)
PCON
0x87 All Pages _{Power Control}
PMU0CF
0xB5
0x0 _{PMU0 Configuration 0}
PMU0FL
0xB6
0x0 PMU0 flag
Page
332
333
321
322
324
323
480
485
485
485
485
485
485
485
485
485
485
485
485
483
483
483
483
483
483
484
484
481
482
260
261
268
265
266
Rev. 1.0
229