C8051F960-B-GM Datasheet, PDF (328/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 25.10. PC0CTR1H: PC0 Counter 1 High (MSB)
Bit
7
6
5
4
3
2
1
0
Name
PC0CTR1H[23:16]
Type
R
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xDF; SFR Page = 0x2
Bit
Name
7:0 PC0CTR1H[23:16] PC0 Counter 1 High Byte
Bits 23:16 of Counter 1.
Function
SFR Definition 25.11. PC0CTR1M: PC0 Counter 1 Middle
Bit
7
6
5
4
3
2
1
0
Name
PC0CTR1M[15:8]
Type
R
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xDE; SFR Page = 0x2
Bit
Name
7:0 PC0CTR1M[15:8] PC0 Counter 1 Middle Byte
Bits 15:8 of Counter 1.
Function
SFR Definition 25.12. PC0CTR1L: PC0 Counter 1 Low (LSB)
Bit
7
6
5
4
3
2
1
0
Name
PC0CTR1L[7:0]
Type
R
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xDD; SFR Page = 0x2
Bit
Name
7:0 PC0CTR1L[7:0] PC0 Counter 1 Low Byte
Bits 7:0 of Counter 1.
Function
Note: PC0CTR1L must be read before PC0CTR1M and PC0CTR1H to latch the count for reading.
328
Rev. 1.0