C8051F960-B-GM Datasheet, PDF (160/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
12. Cyclic Redundancy Check Unit (CRC0)
C8051F96x devices include a cyclic redundancy check unit (CRC0) that can perform a CRC using a 16-bit
or 32-bit polynomial. CRC0 accepts a stream of 8-bit data written to the CRC0IN register. CRC0 posts the
16-bit or 32-bit result to an internal register. The internal result register may be accessed indirectly using
the CRC0PNT bits and CRC0DAT register, as shown in Figure 12.1. CRC0 also has a bit reverse register
for quick data manipulation.
CRC0IN
8
8 _{Automatic CRC}
Controller
Flash
Memory
CRC0SEL
CRC0INIT
CRC0VAL
CRC0PNT1
CRC0PNT0
CRC0FLIP
Write
CRC Engine
32
RESULT
8
88
8
CRC0AUTO
CRC0CNT
4 to 1 MUX
CRC0FLIP
Read
8
CRC0DAT
Figure 12.1. CRC0 Block Diagram
12.1. 16-bit CRC Algorithm
The C8051F96x CRC unit calculates the 16-bit CRC MSB-first, using a poly of 0x1021. The following
describes the 16-bit CRC algorithm performed by the hardware:
1. XOR the most-significant byte of the current CRC result with the input byte. If this is the first iteration
of the CRC unit, the current CRC result will be the set initial value (0x0000 or 0xFFFF).
a. If the MSB of the CRC result is set, left-shift the CRC result, and then XOR the CRC result with
the polynomial (0x1021).
b. If the MSB of the CRC result is not set, left-shift the CRC result.
2. Repeat at Step 2a for the number of input bits (8).
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Rev. 1.0