C8051F960-B-GM Datasheet, PDF (148/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Data transfer size DMA0NSZH:L defines the maximum number of bytes for the DMA0 transfer of the
selected channel. If the address offset reaches data transfer size, the full-length interrupt flag bit CHn_INT
(DMA0INT) of the selected channel will be asserted. Similarly, the mid-point interrupt flag bit CHn_MINT is
set when the address offset is equal to half of data transfer size if the transfer size is an even number or
when the address offset is equal to half of the transfer size plus one if the transfer size is an odd number.
Interrupt flags must be cleared by software so that the next DMA0 data transfer can proceed.
The DMA0 subsystem permits data transfer between SFR registers and XRAM. The DMA0 subsystem
executes its task based on settings of a channel’s control and memory interface configuration SFRs. When
data is copied from XRAM to SFR registers, it takes two cycles for DMA0 to read from XRAM and the SFR
write occurs in the second cycle. If more than one byte is involved, a pipeline is used. When data is copied
from SFR registers to XRAM, the DMA0 only requires one cycle for one byte transaction.
The selected DMA0 channel for a peripheral should be enabled through the enable bits CHn_EN
(DMA0EN.n) to allow the DMA0 to transfer the data. When the DMA0 is transferring data on a channel, the
busy status bit of the channel CHn_BUSY (DMA0BUSY.n) is set. During the transaction, writes to
DMA0NSZH:L, DMA0NBAH:L, and DMA0NAOH:L are disabled.
Each peripheral is responsible for asserting the peripheral transfer requests necessary to service the par-
ticular peripheral. Some peripherals may have a complex state machine to manage the peripheral
requests. Please refer to the DMA enabled peripheral chapters for additional information (AES0, CRC1,
ENC0 and SPI1).
Besides reporting transaction status of a channel, DMA0BUSY can be used to force a DMA0 transfer on
an already configured channel by setting the CHn_BUSY bit (DMA0BUSY.n).
The DMA0NMD sfr has a wrap bit that supports address offset wrapping. The size register DMA0NSZ sets
the transfer size. Normally the address offset starts at zero and increases until it reaches size minus one.
At this point the transfer is complete and the interrupt bit will be set. When the wrap bit is set, the address
offset will automatically be reset to zero and transfers will continue as long as the peripheral keeps
requesting data.
The wrap feature can be used to support key wrapping for the AES0 module. Normally the same key is
used over and over with additional data blocks. So the wrap bit should be set when using the XRAM to
AES0KIN request. This feature supports multiple-block encryption operations.
11.2. DMA0 Arbitration
11.2.1. DMA0 Memory Access Arbitration
If both DMA0 and CPU attempt to access SFR register or XRAM at the same time, the CPU pre-empts the
DMA0 module. DMA0 will be stalled until CPU completes its bus activity.
11.2.2. DMA0 Channel Arbitration
Multiple DMA0 channels can request transfer simultaneously, but only one DMA0 channel will be granted
the bus to transfer the data. Channel 0 has the highest priority. DMA0 channels are serviced based on their
priority. A higher priority channel is serviced first. Channel arbitration occurs at the end of the data transfer
granularity (transaction boundary) of the DMA. When there is a DMA0 request at the transaction boundary
from higher priority channel, lower priority ones will be stalled until the highest priority one completes its
transaction. So, for 16-bit transfers, the transaction boundary is at every 2 bytes.
11.3. DMA0 Operation in Low Power Modes
DMA0 remains functional in normal active, low power active, idle, low power idle modes but not in sleep or
suspend mode. CPU will wait for DMA0 to complete all pending requests before it enters sleep mode.
When the system wakes up from suspend or sleep mode to normal active mode, pending DMA0 interrupts
will be serviced according to priority of channels. DMA0 stalls when CPU is in debug mode.
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