C8051F960-B-GM Datasheet, PDF (311/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Internal Register Definition 24.10. ALARM1Bn: SmaRTClock Alarm 1 Match Value
Bit
7
6
5
4
3
2
1
0
Name
ALARM1[31:0]
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SmaRTClock Address: ALARM1B0 = 0x0C; ALARM1B1 = 0x0D; ALARM1B2 = 0x0E; ALARM1B3 = 0x0F
Bit
Name
Function
7:0 ALARM1[31:0] SmaRTClock Alarm 1 Programmed Value.
These 4 registers (ALARM1B3–ALARM1B0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (ALRM1EN=0)
when updating these registers.
Note: The least significant bit of the alarm programmed value is iALARM1B0.0.
Internal Register Definition 24.11. ALARM2Bn: SmaRTClock Alarm 2 Match Value
Bit
7
6
5
4
3
2
1
0
Name
ALARM2[31:0]
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SmaRTClock Address: ALARM2B0 = 0x10; ALARM2B1 = 0x11; ALARM2B2 = 0x12; ALARM2B3 = 0x13
Bit
Name
Function
7:0 ALARM2[31:0] SmaRTClock Alarm 2 Programmed Value.
These 4 registers (ALARM2B3–ALARM2B0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (ALRM2EN=0)
when updating these registers.
Note: The least significant bit of the alarm programmed value is ALARM2B0.0.
Rev. 1.0
311