C8051F960-B-GM Datasheet, PDF (256/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 18.7. FRBCN: Flash Read Buffer Control
Bit
7
6
5
4
3
2
Name
Type
R
R
R
R
R
R
Reset
0
0
1
0
0
0
SFR Page = 0xF; SFR Address = 0xB5
Bit Name
Function
7:2 Unused Read = 000000b. Write = don’t care.
1
FRBD Flash Read Buffer Disable Bit.
0: Flash read buffer is enabled and being used.
1: Flash read buffer is disabled and bypassed.
0 CHBLKW Block Write Enable Bit.
This bit allows block writes to flash memory from firmware.
0: Each byte of a software flash write is written individually.
1: Flash bytes are written in groups of four.
1
FRBD
R/W
0
0
CHBLKW
R/W
0
256
Rev. 1.0