C8051F960-B-GM Datasheet, PDF (240/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 17.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
3
2
1
0
Name EAES0 EENC0 EDMA0 EPC0
ESPI1 ERTC0F EMAT EWARN
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages;SFR Address = 0xE7
Bit Name
Function
7 EAES0 Enable AES0 Interrupt.
This bit sets the masking of AES0 interrupts.
0: Disable all AES0 interrupts.
1: Enable interrupt requests generated by AES0.
6 EENC0 Enable Encoder (ENC0) Interrupt.
This bit sets the masking of ENC0 interrupts.
0: Disable all ENC0 interrupts.
1: Enable interrupt requests generated by ENC0.
5 EDMA0 Enable DMA0 Interrupt.
This bit sets the masking of DMA0 interrupts.
0: Disable all DMA0 interrupts.
1: Enable interrupt requests generated by DMA0.
4
EPC0 Enable Pulse Counter (PC0) Interrupt.
This bit sets the masking of PC0 interrupts.
0: Disable all PC0 interrupts.
1: Enable interrupt requests generated by PC0.
3 ESPI1 Enable Serial Peripheral Interface (SPI1) Interrupt.
This bit sets the masking of the SPI1 interrupts.
0: Disable all SPI1 interrupts.
1: Enable interrupt requests generated by SPI1.
2 ERTC0F Enable SmaRTClock Oscillator Fail Interrupt.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by SmaRTClock Alarm.
1 EMAT Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
0 EWARN Enable VDD/DC+ Supply Monitor Early Warning Interrupt.
This bit sets the masking of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: Disable the VDD/DC+ Supply Monitor Early Warning interrupt.
1: Enable interrupt requests generated by VDD/DC+ Supply Monitor.
240
Rev. 1.0