C8051F960-B-GM Datasheet, PDF (235/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

Interrupt Source
Table 17.1. Interrupt Summary
Interrupt Priority
Vector Order
Pending Flag
C8051F96x
Enable
Flag
Priority
Control
SmaRTClock Oscillator
Fail
0x008B 17
OSCFAIL
(RTC0CN.5)²
N N ERTC0F PFRTC0F
(EIE2.2) (EIP2.2)
SPI1
0x0093
18
SPIF (SPI1CN.7) N N ESPI1
PSPI1
WCOL (SPI1CN.6)
(EIE2.3) (EIP2.3)
MODF (SPI1CN.5)
RXOVRN (SPI1CN.4)
Pulse Counter
0x009B 19
C0ZF (PC0CN.4)
C1ZF (PC0CN.6)
N N EPC0
PPC0
(EIE2.4) (EIP2.4)
DMA0
0x00A3 20
DMAINT0...7
DMAMINT0...7
N N EDMA0 PDMA0
(EIE2.5) (EIP2.5)
Encoder0
0x00AB 21 ENCERR(ENCCN.6) N N EENC0 PENC0
(EIE2.6) (EIP2.6)
AES
0x00B3 22
AESDONE
(AESBCF.5)
N N EAES0 PAES0
(EIE2.7) (EIP2.7)
Notes:
1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from
vectoring to the associated interrupt service routine.
2. Indicates a register located in an indirect memory space.
17.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described in the following
register descriptions. Refer to the data sheet section associated with a particular on-chip peripheral for
information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending
flag(s).
Rev. 1.0
235