C8051F960-B-GM Datasheet, PDF (366/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 27.12. P0DRV: Port0 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
P0DRV[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xA4
Bit Name
Function
7:0 P0DRV[7:0] Drive Strength Configuration Bits for P0.7–P0.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P0.n Output has low output drive strength.
1: Corresponding P0.n Output has high output drive strength.
SFR Definition 27.13. P1: Port1
Bit
7
6
5
4
3
2
1
0
Name
P1[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = All Pages; SFR Address = 0x90; Bit-Addressable
Bit Name
Description
Write
Read
7:0 P1[7:0] Port 1 Data.
0: Set output latch to logic 0: P1.n Port pin is logic
Sets the Port latch logic
LOW.
LOW.
value or reads the Port pin ^{1: Set output latch to logic 1: P1.n Port pin is logic}
logic state in Port cells con- ^HIGH.
HIGH.
figured for digital I/O.
366
Rev. 1.0