C8051F960-B-GM Datasheet, PDF (266/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 19.5. PMU0FL: Power Management Unit Flag^1,2
Bit
7
6
5
4
3
2
1
0
Name
BATMWK Reserved PC0WK
Type R
R
R
R
R
R/W
R/W
R/W
Reset 0
0
0
0
0
0
0
Varies
SFR Page = 0x0; SFR Address = 0xB6
Bit Name
Description
Write
Read
7:3 Unused Unused
Don’t Care.
0000000
2 BATMWK VBAT Monitor (inside 0: Disable wake-up on Set to 1 if VBAT Monitor
LCD Logic) Wake-up
VBAT Monitor event.
event caused the last
Source Enable and Flag _{1: Enable wake-up on CS0} wake-up.
event.
1 Reserved Reserved
Must write 0.
Always reads 0.
0 PC0WK Pulse Counter Wake-up 0: Disable wake-up on Set to 1 if PC0 event
Source Enable and Flag PC0 event.
caused the last wake-up.
1: Enable wake-up on PC0
event.
Notes:
1. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in suspend or sleep
mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
2. PMU0 requires two system clocks to update the wake-up source flags after waking from suspend mode. The
wake-up source flags will read 0 during the first two system clocks following the wake from suspend mode.
266
Rev. 1.0