C8051F960-B-GM Datasheet, PDF (279/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
22.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin voltage tracks the supply voltage
(through a weak pull-up) until the device is released from reset. After the supply settles above VPOR, a
delay occurs before the device is released from reset; the delay decreases as the supply ramp time
increases (ramp time is defined as how fast the supply ramps from 0 V to V_POR). Figure 22.2 plots the
power-on and supply monitor reset timing. For valid ramp times (less than 3 ms), the power-on reset delay
(T_PORDelay) is typically 7 ms (V_DD = 1.8 V) or 15 ms (V_DD = 3.6 V).
Note: The maximum supply ramp time is 3 ms; slower ramp times may cause the device to be released from reset
before the supply reaches the V_POR level.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
The POR supply monitor will continue to monitor the VBAT supply, even in Sleep Mode, to reset the sys-
tem if the supply voltage drops below VPOR. It can be disabled to save power by writing 1 to the MONDIS
(PMU0MD.5) bit. When the POR supply monitor is disabled, all reset sources will trigger a full POR and will
re-enable the POR supply monitor.
Supply voltage
V_POR
See specification
table for min/max
voltages.
RST
Logic HIGH
Logic LOW
T_PORDelay
t
T_PORDelay
Power-On
Reset
Power-On
Reset
Figure 22.2. Power-On Reset Timing Diagram
Rev. 1.0
279