C8051F960-B-GM Datasheet, PDF (309/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Internal Register Definition 24.7. RTC0CF: SmaRTClock Configuration
Bit
7
Name
Type R/W
Reset
0
6
ALRM2
R/W
0
5
ALRM1
R/W
0
4
ALRM0
R/W
0
3
2
AUTORST RTC2EN
R/W
R/W
0
0
1
RTC1EN
R/W
0
0
RTC0EN
R/W
0
SmaRTClock Address = 0x07
Bit Name
7 Reserved Read = 0b; Must write 0b.
Function
6 ALRM2 Event Flag for Alarm 2.
This bit must be cleared by software. Writing a ‘1’ to this bit has no effect.
0: An Alarm 2 event has not occured since the last time the flag was cleared.
1: An Alarm 2 event has occured.
5 ALRM1 Event Flag for Alarm 1.
This bit must be cleared by software. Writing a ‘1’ to this bit has no effect.
0: An Alarm 1 event has not occured since the last time the flag was cleared.
1: An Alarm 1 event has occured.
4 ALRM0 Event Flag for Alarm 0.
This bit must be cleared by software. Writing a ‘1’ to this bit has no effect.
0: An Alarm 0 event has not occured since the last time the flag was cleared.
1: An Alarm 0 event has occured.
3 AUTORST Auto Reset Enable.
Enables the Auto Reset function to clear the counter when an Alarm 0 event occurs.
0: Auto Reset is disabled
1: Auto Reset is enabled.
2 RTC2EN Alarm 2 Enable.
0: Alarm 2 is disabled.
1: Alarm 2 is enabled.
1 RTC1EN Alarm 1 Enable.
0: Alarm 1 is disabled.
1: Alarm 1 is enabled.
0 RTC0EN Alarm 0 Enable.
0: Alarm 0 is disabled.
1: Alarm 0 is enabled.
Rev. 1.0
309