C8051F960-B-GM Datasheet, PDF (273/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 20.1. DC0CN: DC-DC Converter Control
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
CLKSEL
R
0
CLKDIV[1:0]
R/W
R/W
0
0
AD0CKINV
R/W
0
CLKINV
R/W
0
SYNC
R/W
0
MINPW[1:0]
R/W
1
1
SFR Page = 0x0; SFR Address = 0x97
Bit Name
Function
7 CLKSEL _{DC-DC Converter Clock Source Select.}
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
6:5 CLKDIV[1:0] _{DC-DC Clock Divider.}
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. Ignored all other times.
00: The dc-dc converter clock is system clock divided by 1.
01: The dc-dc converter clock is system clock divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is system clock divided by 8.
4 AD0CKINV ADC0 Clock Inversion (Clock Invert During Sync).
Inverts the ADC0 SAR clock derived from the dc-dc converter clock when the SYNC
bit (DC0CN.3) is enabled. This bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
3 CLKINV _{DC-DC Converter Clock Invert.}
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
2
SYNC ADC0 Synchronization Enable.
When synchronization is enabled, the ADC0SC[4:0] bits in the ADC0CF register
must be set to 00000b.
0: The ADC is not synchronized to the dc-dc converter.
1: The ADC is synchronized to the dc-dc converter. ADC0 tracking is performed
during the longest quiet time of the dc-dc converter switching cycle and ADC0 SAR
clock is also synchronized to the dc-dc converter switching cycle.
1:0 MINPW[1:0] _{DC-DC Converter Minimum Pulse Width.}
Specifies the minimum pulse width.
00: Minimum pulse detection logic is disabled (no pulse skipping).
01: Minimum pulse width is 10 ns.
10: Minimum pulse width is 20 ns.
11: Minimum pulse width is 40 ns.
Rev. 1.0
273