C8051F960-B-GM Datasheet, PDF (157/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 11.8. DMA0NBAH: Memory Base Address High Byte
Bit
7
6
5
4
3
2
1
0
Name
NBAH[3:0]
Type
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xCB
Bit
Name
Function
7:4
Unused
Read = 0b, Write = Don’t Care
3:0
NBAH[3:0] Memory Base Address High Byte.
Sets high byte of the memory base address which is the DMA0 XRAM start-
ing address of the selected channel if the channel’s address offset
DMA0NAO is reset to 0.
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
SFR Definition 11.9. DMA0NBAL: Memory Base Address Low Byte
Bit
7
6
5
4
3
2
1
0
Name
NBAL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xCA
Bit
Name
Function
7:0
NBAL[7:0]
Memory Base Address Low Byte.
Sets low byte of the memory base address which is the DMA0 XRAM start-
ing address of the selected channel if the channel’s address offset
DMA0NAO is reset to 0.
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
Rev. 1.0
157