C8051F960-B-GM Datasheet, PDF (135/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
A[15:0]
E
M
I
D[7:0]
F
WR
RD
ADDRESS BUS
V_DD
(Optional)
8
DATA BUS
A[15:0]
64 K X 8
SRAM
I/O[7:0]
CE
WE
OE
Figure 10.2. Non-multiplexed Configuration Example
10.5. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 10.3, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 10.2). These modes are summarized below.
More information about the different modes can be found in Section “10.6. Timing” on page 137.
EMI0CF[3:2] = 00
On-Chip XRAM
EMI0CF[3:2] = 01
0xFFFF
EMI0CF[3:2] = 10
0xFFFF
EMI0CF[3:2] = 11
0xFFFF
0xFFFF
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
Off-Chip
Memory
(No Bank Select)
Off-Chip
Memory
(Bank Select)
Off-Chip
Memory
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
0x0000
0x0000
0x0000
Figure 10.3. EMIF Operating Modes
0x0000
Rev. 1.0
135