C8051F960-B-GM Datasheet, PDF (156/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 11.7. DMA0NCF: DMA Channel Configuration
Bit
7
6
5
4
3
Name INTEN MINTEN STALL ENDIAN
Type
R/W
R/W
R/W
R/W
R
Reset
0
0
0
0
0
2
1
0
PERIPH[3:0]
R/W
0
0
0
SFR Page = 0x2; SFR Address = 0xC9
Bit
Name
Function
7
INTEN
Full-Length Interrupt Enable.
0: Disable the full-length interrupt of the selected channel.
1: Enable the full-length interrupt of the selected channel.
6
MINTEN
Mid-Point Interrupt Enable.
0: Disable the mid-point interrupt of the selected channel.
1: Enable the mid-point interrupt of the selected channel.
5
STALL
DMA0 Stall.
Setting this bit stalls the DMA0 transfer on the selected channel. After a
Stall, this bit must be cleared by software to resume normal operation.
0: The DMA0 transfer of the selected channel is not being stalled.
1: The DMA0 transfer of the selected channel is stalled.
4
ENDIAN
Data Transfer Endianness.
This bit sets the byte order for multi-byte transfers. This is only relevant for
two or three byte transfers. The value of this bit does not matter for single
byte transfers.
0: Little Endian
1: Big Endian
3:0
PERIPH[2:0] Peripheral Selection of The Selected Channel.
These bits choose one of the nine DMA0 transfer functions for the selected
channel.
0000: XRAM to ENC0L/M/H
0001: ENC0L/M/H sfrs to XRAM
0010: XRAM to CRC1IN sfr
0011: XRAM to SPI1DAT sfr
0100: SPI1DAT sfr to XRAM
0101: XRAM to AES0KIN sfr
0110: XRAM to AES0BIN sfr
0111: XRAM to AES0XIN sfr
1000: AES0YOUT sfr to XRAM
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
156
Rev. 1.0