C8051F960-B-GM Datasheet, PDF (479/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 33.3. Watchdog Timer Timeout Intervals¹
System Clock (Hz)
PCA0CPL5 Timeout Interval (ms)
24,500,000
255
32.1
24,500,000
128
16.2
24,500,000
32
4.1
3,062,500²
255
257
3,062,500²
128
129.5
3,062,500²
32
33.1
32,000
255
24576
32,000
128
12384
32,000
32
3168
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by 8.
Rev. 1.0
479