C8051F960-B-GM Datasheet, PDF (199/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
14.6.5.1. CTR Data Flow
The AES0 module data flow for CTR encryption and decryption shown in Figure 14.5. The data flow is the
same for encryption and decryption. The AES0DCF sfr is always configured to XOR AES0XIN with the
AES Core output.The XOR on the input is not used. The AES core is configured for an encryption opera-
tion. The encryption key is written to AES0KIN. The key size is set to the desired key size.
For an encryption operation, the plaintext is written to the AES0BIN sfr and the ciphertext is read from
AES0YOUT. For decryption, the ciphertext is written to AES0BIN and the plaintext is read from
AES0YOUT.
Note the counter must be incremented after each block using software.
AES0BIN
internal state
machine
AES0XIN
+
AES0DCFG
AES0KIN
Data In
Key
AES
Key
In
Core
Out
Data Out
AES0BCFG
+
AES0YOUT
Figure 14.8. Counter Mode Data Flow
Rev. 1.0
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