C8051F960-B-GM Datasheet, PDF (342/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 26.4. LCD0MSCN: LCD0 Master Control
Bit
7
Name
Type ^R/W
Reset
0
6
5
4
BIASEN DCBIASOE CLKOE
R/W
R/W
R/W
0
1
0
3
2
1
0
LOWDRV LCDRST LCDEN
R/W
R/W
R/W
R/W
0
0
0
0
SFR Page = 0x2; SFR Address = 0xAB
Bit
Name
Function
7 Reserved Read = 0b. Must write 0b.
6
BIASEN _{LCD0 Bias Enable.}
LCD0 bias may be disabled when using a static LCD (single backplane), contrast
control mode 1 (Bypass Mode) is selected, and the VLCD/VIO Supply Comparator
is disabled (LCD0CF.5 = 1). It is required for all other modes.
0: LCD0 Bias is disabled.
1: LCD0 Bias is enabled
5 DCBIASOE _{DCDC Converter Bias Output Enable. (Note 1)}
0: The bias for the DCDC converter is gated off.
1: LCD0 provides the bias for the DCDC converter.
4
CLKOE _{LCD Clock Output Enable.}
0: The clock signal to the LCD0 module is gated off.
1: The SmaRTClock provides the undivided clock to the LCD0 Module.
3 Reserved Read = 0b. Must write 0b.
2
LOWDRV _{Charge Pump Reduced Drive Mode.}
This bit should be set to 1 in Contrast Control Mode 3 and Mode 4 for minimum
power consumption. This bit may be set to 0 in these modes to support higher load
current requirements.
0: The charge pump operates at full power.
1: The charge pump operates at reduced power.
1
LCDRST _{LCD0 Reset.}
Writing a 1 to this bit will clear all the LCD0Dn registers to 0x00. This bit must be
cleared by software.
0
LCDEN LCD0 Enable.
0: LCD0 is disabled.
1: LCD0 is enabled.
Note 1: To same bias generator is shared by the DCDC Converter and LCD0.
342
Rev. 1.0