C8051F960-B-GM Datasheet, PDF (303/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
ness. As shown in Figure 24.2, duty cycles less than 65% indicate a robust oscillation. As the duty cycle
approaches 68%, oscillation becomes less reliable and the risk of clock failure increases. Increasing the
bias current (by disabling AGC) will always improve oscillation robustness and will reduce the output
clock’s duty cycle. This test should be performed at the worst case system conditions, as results at very
low temperatures or high supply voltage will vary from results taken at room temperature or low supply
voltage.
Safe Operating Zone
Low Risk of Clock High Risk of Clock
Failure
Failure
25%
65%
68%
Duty Cycle
Figure 24.2. Interpreting Oscillation Robustness (Duty Cycle) Test Results
As an alternative to performing the oscillation robustness test, Automatic Gain Control may be disabled at
the cost of increased power consumption (approximately 200 nA). Disabling Automatic Gain Control will
provide the crystal oscillator with higher immunity against external factors which may lead to clock failure.
Automatic Gain Control must be disabled if using the SmaRTClock oscillator in self-oscillate mode.
Table 24.3 shows a summary of the oscillator bias settings. The SmaRTClock Bias Doubling feature allows
the self-oscillation frequency to be increased (almost doubled) and allows a higher crystal drive strength in
crystal mode. High crystal drive strength is recommended when the crystal is exposed to poor environmen-
tal conditions such as excessive moisture. SmaRTClock Bias Doubling is enabled by setting BIASX2
(RTC0XCN.5) to 1.
.
Table 24.3. SmaRTClock Bias Settings
Mode
Crystal
Self-Oscillate
Setting
Power
Consumption
Bias Double Off, AGC On
Lowest
Bias Double Off, AGC Off
Low
Bias Double On, AGC On
High
Bias Double On, AGC Off
Highest
Bias Double Off
Low
Bias Double On
High
Rev. 1.0
303