C8051F960-B-GM Datasheet, PDF (261/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 19.2. PCLKEN: Peripheral Clock Enable
Bit
7
6
5
4
3
2
1
0
Name
PCLKEN[3:0]
Type R/W
R/W
R/W
R/W
R/W
Reset
SFR Page = 0xF; SFR Address = 0xFE
Bit Name
Function
7:4 Unused Read = 0b; Write = don’t care.
3 PCLKEN3 Clock Enable Controls for Peripherals in Low Power Idle Mode.
0: Disable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Idle
Mode.
1: Enable clocks to the SmaRTClock, Pulse Counter, and PMU0 in Low Power Idle
Mode.
2 PCLKEN2 Clock Enable Controls for Peripherals in Low Power Idle Mode.
0: Disable clocks to Timer 0, Timer 1, Timer 2, and CRC0 in Low Power Idle Mode.
1: Enable clocks to Timer 0, Timer 1, Timer 2, and CRC0 in Low Power Idle Mode.
1 PCLKEN1 Clock Enable Controls for Peripherals in Low Power Idle Mode.
0: Disableclocks to ADC0 and PCA0 in Low Power Idle Mode.
1: Enable clocks to ADC0 and PCA0 in Low Power Idle Mode.
0 PCLKEN0 Clock Enable Controls for Peripherals in Low Power Idle Mode.
0: Disable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Idle Mode.
1: Enable clocks to UART0, Timer 3, SPI0, and the SMBus in Low Power Idle Mode.
Rev. 1.0
261