C8051F960-B-GM Datasheet, PDF (339/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
26.3.2. Contrast Control Mode 2 (Minimum Contrast Mode)
In Contrast Control Mode 2, a minimum contrast voltage is maintained, as shown in Figure 26.4. The
VLCD supply is powered directly from VBAT as long as VBAT is higher than the programmable VBAT mon-
itor threshold voltage. As soon as the VBAT supply monitor detects that VBAT has dropped below the pro-
grammed value, the charge pump will be automatically enabled in order to acheive the desired minimum
contrast voltage on VLCD. Minimum Contrast Mode is selected using the following procedure:
1. Clear Bit 2 of the LCD0MSCN register to 0b (LCD0MSCN &= ~0x04)
2. Set Bit 0 of the LCD0MSCF register to 1b (LCD0MSCF |= 0x01)
3. Set Bit 3 of the LCD0PWR register to 1b (LCD0PWR |= 0x08)
4. Set Bit 7 of the LCD0VBMCN register to 1b (LCD0VBMCN |= 0x80)
VBAT
VLCD
Figure 26.4. Contrast Control Mode 2
26.3.3. Contrast Control Mode 3 (Constant Contrast Mode)
In Contrast Control Mode 3, a constant contrast voltage is maintained. The VLCD supply is regulated to the
programmed contrast voltage using a variable resistor between VBAT and VLCD as long as VBAT is
higher than the programmable VBAT monitor threshold voltage. As soon as the VBAT supply monitor
detects that VBAT has dropped below the programmed value, the charge pump will be automatically
enabled in order to acheive the desired contrast voltage on VLCD. Constant Contrast Mode is selected
using the following procedure:
1. Set Bit 2 of the LCD0MSCN register to 1b (LCD0MSCN |= 0x04)
2. Clear Bit 0 of the LCD0MSCF register to 0b (LCD0MSCF &= ~0x01)
3. Set Bit 3 of the LCD0PWR register to 1b (LCD0PWR |= 0x08)
4. Set Bit 7 of the LCD0VBMCN register to 1b (LCD0VBMCN |= 0x80)
VBAT
VLCD
Figure 26.5. Contrast Control Mode 3
Rev. 1.0
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