C8051F960-B-GM Datasheet, PDF (306/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Internal Register Definition 24.4. RTC0CN: SmaRTClock Control
Bit
Name
Type
Reset
7
RTC0EN
R/W
0
6
MCLKEN
R/W
0
5
OSCFAIL
R/W
Varies
4
RTC0TR
R/W
0
3
2
1
0
HSMODE RTC0SET RTC0CAP
R/W
R/W
R/W
R/W
0
0
0
0
SmaRTClock Address = 0x04
Bit Name
Function
7 RTC0EN SmaRTClock Enable.
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
6 MCLKEN Missing SmaRTClock Detector Enable.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
5 OSCFAIL SmaRTClock Oscillator Fail Event Flag.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be
cleared by software. The value of this bit is not defined when the SmaRTClock 
oscillator is disabled.
4 RTC0TR SmaRTClock Timer Run Control.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock timer is stopped.
1: SmaRTClock timer is running.
3 Reserved Read = 0b; Must write 0b.
2 HSMODE High Speed Mode Enable.
Should be set to 1 if the system clock is faster than 4x the SmaRTClock frequency.
0: High Speed Mode is disabled.
1: High Speed Mode is enabled.
1 RTC0SET SmaRTClock Timer Set.
Writing 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hard-
ware to indicate that the timer set operation is complete.
0 RTC0CAP SmaRTClock Timer Capture.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by
hardware to indicate that the timer capture operation is complete.
306
Rev. 1.0