C8051F960-B-GM Datasheet, PDF (36/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Name
P0.0
V_REF
P0.1
AGND
P0.2
XTAL1
P0.3
XTAL2
P0.4
TX
P0.5
RX
Table 3.1. Pin Definitions for the C8051F96x (Continued)
Pin Numbers
DQFN76 TQFP80 QFN40
A4
6
4
Type Description
D I/O or Port 0.0. See Port I/O Section for a complete
A In description.
A3
4
A In
A Out
External V_REF Input.
Internal V_REF Output. External V_REF decoupling
capacitors are recommended. See ADC0 Section
for details.
3 D I/O or Port 0.1. See Port I/O Section for a complete
A In description.
A2
2
G
Optional Analog Ground. See ADC0 Section for
details.
2 D I/O or Port 0.2. See Port I/O Section for a complete
A In description.
A1
1
A In
External Clock Input. This pin is the external
oscillator return for a crystal or resonator. See
Oscillator Section.
1 D I/O or Port 0.3. See Port I/O Section for a complete
A In description.
A40
79
A Out
D In
A In
External Clock Output. This pin is the excitation
driver for an external crystal or resonator.
External Clock Input. This pin is the external
clock input in external CMOS clock mode.
External Clock Input. This pin is the external
clock input in capacitor or RC oscillator configu-
rations.
See Oscillator Section for complete details.
40 D I/O or Port 0.4. See Port I/O Section for a complete
A In description.
A39
78
D Out
UART TX Pin. See Port I/O Section.
39 D I/O or Port 0.5. See Port I/O Section for a complete
A In description.
D In
UART RX Pin. See Port I/O Section.
36
Rev. 1.0