C8051F960-B-GM Datasheet, PDF (10/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
List of Figures
Figure 1.1. C8051F960 Block Diagram ................................................................... 23
Figure 1.2. C8051F961 Block Diagram ................................................................... 23
Figure 1.3. C8051F962 Block Diagram ................................................................... 24
Figure 1.4. C8051F963 Block Diagram ................................................................... 24
Figure 1.5. C8051F964 Block Diagram ................................................................... 25
Figure 1.6. C8051F965 Block Diagram ................................................................... 25
Figure 1.7. C8051F966 Block Diagram ................................................................... 26
Figure 1.8. C8051F967 Block Diagram ................................................................... 26
Figure 1.9. C8051F968 Block Diagram ................................................................... 27
Figure 1.10. C8051F969 Block Diagram ................................................................. 27
Figure 1.11. Port I/O Functional Block Diagram ...................................................... 29
Figure 1.12. PCA Block Diagram ............................................................................. 30
Figure 1.13. ADC0 Functional Block Diagram ......................................................... 31
Figure 1.14. ADC0 Multiplexer Block Diagram ........................................................ 32
Figure 1.15. Comparator 0 Functional Block Diagram ............................................ 33
Figure 1.16. Comparator 1 Functional Block Diagram ............................................ 33
Figure 3.1. DQFN-76 Pinout Diagram (Top View) ................................................... 43
Figure 3.2. QFN-40 Pinout Diagram (Top View) ..................................................... 44
Figure 3.3. TQFP-80 Pinout Diagram (Top View) ................................................... 45
Figure 3.4. DQFN-76 Package Drawing .................................................................. 46
Figure 3.5. DQFN-76 Land Pattern ......................................................................... 47
Figure 3.6. Recomended Inner Via Placement ........................................................ 49
Figure 3.7. Typical QFN-40 Package Drawing ........................................................ 50
Figure 3.8. QFN-40 Landing Diagram ..................................................................... 51
Figure 3.9. TQFP-80 Package Drawing .................................................................. 52
Figure 3.10. TQFP80 Landing Diagram .................................................................. 54
Figure 4.1. Frequency Sensitivity (External CMOS Clock, 25°C) ............................ 64
Figure 4.2. Typical VOH Curves, 1.8–3.6 V ............................................................ 66
Figure 4.3. Typical VOL Curves, 1.8–3.6 V ............................................................. 67
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 78
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing 
(BURSTEN = 0) .................................................................................... 81
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 82
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 83
Figure 5.5. ADC Window Compare Example: Right-Justified 
Single-Ended Data ................................................................................ 94
Figure 5.6. ADC Window Compare Example: Left-Justified 
Single-Ended Data ................................................................................ 94
Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 95
Figure 5.8. Temperature Sensor Transfer Function ................................................ 97
Figure 5.9. Temperature Sensor Error with 1-Point Calibration 
(V_REF = 1.68 V) ..................................................................................... 98
Figure 5.10. Voltage Reference Functional Block Diagram ................................... 100
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Rev. 1.0