C8051F960-B-GM Datasheet, PDF (284/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
22.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
 A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a
MOVX write operation targets an address above the Lock Byte address.
 A Flash read is attempted above user code space. This occurs when a MOVC operation targets an
address above the Lock Byte address.
 A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the Lock Byte address.
 A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section
“18.3. Security Options” on page 247).
 A Flash write or erase is attempted while the V_DD Monitor is disabled.
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
22.8. SmaRTClock (Real Time Clock) Reset
The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or SmaRT-
Clock Alarm. The SmaRTClock Oscillator Fail event occurs when the SmaRTClock Missing Clock Detector
is enabled and the SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm event occurs
when the SmaRTClock Alarm is enabled and the SmaRTClock timer value matches the ALARMn regis-
ters. The SmaRTClock can be configured as a reset source by writing a 1 to the RTC0RE flag
(RSTSRC.7). The SmaRTClock reset remains functional even when the device is in the low power Sus-
pend or Sleep mode. The state of the RST pin is unaffected by this reset.
22.9. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
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