C8051F960-B-GM Datasheet, PDF (372/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 27.24. P3MDIN: Port3 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P3MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = 0xF; SFR Address = 0xF1
Bit
Name
Function
7:0 P3MDIN[3:0] Analog Configuration Bits for P3.7–P3.0 (respectively).
Port pins configured for analog mode have their weak pullup and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P3.n pin is configured for analog mode.
1: Corresponding P3.n pin is not configured for analog mode.
SFR Definition 27.25. P3MDOUT: Port3 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P3MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0xB1
Bit
Name
Function
7:0 P3MDOUT[7:0] Output Configuration Bits for P3.7–P3.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Corresponding P3.n Output is push-pull.
372
Rev. 1.0