C8051F960-B-GM Datasheet, PDF (70/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 4.11. SmaRTClock Characteristics
V_BAT = 1.8 to 3.8 V; T_A = –40 to +85 °C unless otherwise specified; Using factory-calibrated settings.
Parameter
Conditions
Min
Typ
Max
Oscillator Frequency (LFO)
13.1
16.4
19.7
Units
kHz
Table 4.12. ADC0 Electrical Characteristics
V_BAT = 1.8 to 3.8 V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min Typ Max Units
DC Accuracy
Resolution
Integral Nonlinearity
Differential Nonlinearity
(Guaranteed Monotonic)
12-bit mode
10-bit mode
12-bit mode¹
10-bit mode
12-bit mode¹
10-bit mode
12
10
bits
—
—
±1
±3
±0.5 ±1
LSB
—
—
±0.8 ±2
±0.5 ±1
LSB
Offset Error
Full Scale Error
12-bit mode
10-bit mode
12-bit mode²
10-bit mode
—
—
±<1
±<1
±3
±3
LSB
—
—
±1
±1
±4
±2.5
LSB
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, maximum
sampling rate)
Signal-to-Noise Plus Distortion³
Signal-to-Distortion³
Spurious-Free Dynamic Range³
12-bit mode
10-bit mode
12-bit mode
10-bit mode
12-bit mode
10-bit mode
62
54
65
—
58
—
dB
—
—
76
—
73
—
dB
—
—
82
—
75
—
dB
Conversion Rate
SAR Conversion Clock
Normal Power Mode
Low Power Mode
—
—
—
—
8.33
4.4
MHz
Conversion Time in SAR Clocks
10-bit Mode
8-bit Mode
13
11
—
—
—
—
clocks
Track/Hold Acquisition Time
Initial Acquisition
1.5
—
—
Subsequent Acquisitions
(dc input, burst mode)
1.1
—
—
us
Throughput Rate
12-bit mode
10-bit mode
—
—
—
—
75
300
ksps
1. INL and DNL specifications for 12-bit mode do not include the first or last four ADC codes.
2. The maximum code in 12-bit mode is 0xFFFC. The Full Scale Error is referenced from the maximum code.
3. Performance in 8-bit mode is similar to 10-bit mode.
70
Rev. 1.0