C8051F960-B-GM Datasheet, PDF (385/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 28.1. SMBus Clock Source Selection
SMBCS1
0
0
1
1
SMBCS0
0
1
0
1
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 28.1. The
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “32. Timers” on page 444.
T_HighMin
=
T_LowMin
=
----------------------1-----------------------
f_{ClockSourceOverflow}
Equation 28.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 28.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 28.1.
BitRate = -^f-^C----^l-^o---^c--^k--^S---^o--^u---^r--^c--^e--^O----^v--^e--^r--^f--^l-^o---^w-
3
Equation 28.2. Typical SMBus Bit Rate
Figure 28.4 shows the typical SCL generation described by Equation 28.2. Notice that T_HIGH is typically
twice as large as T_LOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by Equation 28.2.
Timer Source
Overflows
SCL
T_Low
T_High
SCL High Timeout
Figure 28.4. Typical SMBus SCL Generation
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 28.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Rev. 1.0
385