C8051F960-B-GM Datasheet, PDF (158/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 11.10. DMA0NAOH: Memory Address Offset High Byte
Bit
7
6
5
4
3
2
1
0
Name
NAOH[1:0]
Type
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xCD
Bit
Name
Function
7:2
Unused
Read = 0b, Write = Don’t Care
1:0
NAOH[1:0] Memory Address Offset High Byte.
Sets the high byte of the address offset of the selected channel which acts a
counter during DMA0 transfer. The address offset auto-increments by one
after one byte is transferred. When configuring a channel for DMA0 transfer,
the address offset should be reset to 0.
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
SFR Definition 11.11. DMA0NAOL: Memory Address Offset Low Byte
Bit
7
6
5
4
3
2
1
0
Name
NACL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x2; SFR Address = 0xCC
Bit
Name
Function
7:0
NACL[7:0]
Memory Address Offset Low Byte.
Sets the low byte of the address offset of the selected channel which acts a
counter during DMA0 transfer. The address offset auto-increments by one
after one byte is transferred. When configuring a channel for DMA0 transfer,
the address offset should be reset to 0.
Note: This sfr is a DMA channel indirect register. Select the desired channel first using the DMA0SEL sfr.
158
Rev. 1.0