C8051F960-B-GM Datasheet, PDF (322/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
SFR Definition 25.2. PC0PCF: PC0 Mode Pull-Up Configuration
Bit
7
6
5
4
3
2
1
0
Name PUCAL CALRES CALPORT
RES[2:0]
DUTY[1:0]
Type R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
1
0
0
0
1
0
0
SFR Address = 0xD7; SFR Page = 0x2
Bit
Name
Function
7
PUCAL
Pull-Up Driver Calibration
0: Calibration complete or not running.
1: Start calibration of pull up (Self clearing). 
Calibration determines the lowest usable pull-up strength.
6
CALRES
Calibration Result
0: Fail (switch may be closed preventing detection of pull ups). 
Writes value of 0x11111 to PC0PCF[4:0]
1: Pass (writes calibrated value into PC0PCF[4:0]).
5
CALPORT
Calibration Port
0: Calibration on PC0 only.
1: Calibration on PC1 only.
4:2
RES[2:0]
Pull-Up Resistor Select
Current with force pull-up on bit set (PC0TH.2=1) and VBAT=3.6V.
000: Pull-up disabled.
001: 1 A.*
010: 4 A.*
011: 16 A.*
100: 64 A.*
101: 256 A.*
110: 1 mA.*
111: 4 mA.*
*The effective average pull-up current depends on selected resistor, pull-up
resistor duty-cycle multiplier, and sample rate duty-cycle multiplier.
1:0
DUTY[1:0]
Pull-Up Resistor Duty Cycle Multiplier
000: 1/4 (25%)*
001: 3/8 (37.5%)*
010: 1/2 (50%)*
011: 3/4 (75%)*
*The final pull-up resistor duty cycle is the sample rate duty-cycle multiplier
times the pull-up duty-cycle multiplier.
322
Rev. 1.0