C8051F960-B-GM Datasheet, PDF (278/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
22. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
 CIP-51 halts program execution
 Special Function Registers (SFRs) are initialized to their defined reset values
 External Port pins are forced to a known state
 Interrupts and timers are disabled
All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RAM are unaf-
fected during a reset; any previously stored data is preserved as long as power is not lost. Since the stack
pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are disabled
during the reset and are enabled immediately after exiting reset. For V_DD Monitor resets, the RST pin is
driven low until the device exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. Refer to Section “23. Clocking Sources” on page 286 for information on selecting and configur-
ing the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its
clock source (Section “33.4. Watchdog Timer Mode” on page 477 details the use of the Watchdog Timer).
Program execution begins at location 0x0000.
VBAT
Px.x
Px.x
Supply
Monitor
+
-
Enable
Comparator 0
+
-
C0RSEF
VDC VBAT
switch
Supply
Monitor
+
-
(wired-OR)
Enable
VBAT
Power On
Reset
'0'
SmaRTClock _RTC0RE
Missing
Clock
Detector
(one-
shot)
EN
PCA
WDT
EN
Reset
Funnel
(Software Reset)
SWRSF
Illegal Flash
Operation
System
Clock
CIP-51
Microcontroller
Core
System Reset
Extended Interrupt
Handler
Power Management
Block (PMU0)
Reset
System Reset
Power-On Reset
Figure 22.1. Reset Sources
RST
278
Rev. 1.0