C8051F960-B-GM Datasheet, PDF (103/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
6. Programmable Current Reference (IREF0)
C8051F96x devices include an on-chip programmable current reference (source or sink) with two output
current settings: Low Power Mode and High Current Mode. The maximum current output in Low Power
Mode is 63 µA (1 µA steps) and the maximum current output in High Current Mode is 504 µA (8 µA steps).
The current source/sink is controlled though the IREF0CN special function register. It is enabled by setting
the desired output current to a non-zero value. It is disabled by writing 0x00 to IREF0CN. The port I/O pin
associated with ISRC0 should be configured as an analog input and skipped in the Crossbar. See “Port
Input/Output” on page 351 for more details.
SFR Definition 6.1. IREF0CN: Current Reference Control
Bit
7
6
5
4
3
2
1
0
Name SINK MDSEL
IREF0DAT
Type R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB9
Bit
Name
Function
7
SINK
IREF0 Current Sink Enable.
Selects if IREF0 is a current source or a current sink.
0: IREF0 is a current source.
1: IREF0 is a current sink.
6
MDSEL
IREF0 Output Mode Select.
Selects Low Power or High Current Mode.
0: Low Power Mode is selected (step size = 1 µA).
1: High Current Mode is selected (step size = 8 µA).
5:0 IREF0DAT[5:0] IREF0 Data Word.
Specifies the number of steps required to achieve the desired output current.
Output current = direction x step size x IREF0DAT.
IREF0 is in a low power state when IREF0DAT is set to 0x00.
6.1. PWM Enhanced Mode
The precision of the current reference can be increased by fine tuning the IREF0 output using a PWM sig-
nal generated by the PCA. This mode allows the IREF0DAT bits to perform a course adjustment on the
IREF0 output. Any available PCA channel can perform a fine adjustment on the IREF0 output. When
enabled (PWMEN = 1), the CEX signal selected using the PWMSS bit field is internally routed to IREF0 to
control the on time of a current source having the weight of 2 LSBs. With the two least significant bits of
IREF0DAT set to 00b, applying a 100% duty cycle on the CEX signal will be equivalent to setting the two
LSBs of IREF0DAT to 10b. PWM enhanced mode is enabled and setup using the IREF0CF register.
Rev. 1.0
103