C8051F960-B-GM Datasheet, PDF (35/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
3. Pinout and Package Definitions
Name
VBAT
VBATDC
VDC
GNDDC
GND
IND
VIO
VIORF
RST/
C2CK
P7.0/
Table 3.1. Pin Definitions for the C8051F96x
Pin Numbers
DQFN76 TQFP80 QFN40
A5
8
5
A6
10
5
A8
14
8
A
12
7
B6 13,64,
7
66,68
B5
11
6
B4
9
5
B7
15
8
A9
16
9
A10
17
10
Type Description
P In Battery Supply Voltage. Must be 1.8 to 3.8 V.
P In DC0 Input Voltage. Must be 1.8 to 3.8 V.
P In
P Out
Alternate Power Supply Voltage. Must be 1.8 to
3.6 V. This supply voltage must always be 
VBAT. Software may select this supply voltage to
power the digital logic.
Positive output of the dc-dc converter. A 1 µF to
10 µF ceramic capacitor is required on this pin
when using the dc-dc converter. This pin can
supply power to external devices when the dc-dc
converter is enabled.
P In DC-DC converter return current path. This pin is
typically tied to the ground plane.
G Required Ground.
P In
P In
P In
D I/O
D I/O
D I/O
DC-DC Inductor Pin. This pin requires a 560 nH
inductor to VDC if the dc-dc converter is used.
I/O Power Supply for P0.0–P1.4 and P2.4–P7.0
pins. This supply voltage must always be 
 VBAT.
I/O Power Supply for P1.5–P2.3 pins. This sup-
ply voltage must always be  VBAT.
Device Reset. Open-drain output of internal POR
or V_DD monitor. An external source can initiate a
system reset by driving this pin low for at least
15 µs. A 1 k to 5 k pullup to V_DD is recom-
mended. See Reset Sources Section for a com-
plete description.
Clock signal for the C2 Debug Interface.
Port 7.0. This pin can only be used as GPIO. The
Crossbar cannot route signals to this pin and it
cannot be configured as an analog input. See
Port I/O Section for a complete description.
C2D
VLCD
A32
61
D I/O ^{Bi-directional data signal for the C2 Debug Inter-}
face.
32
P I/O LCD Power Supply. This pin requires a 10 µF
capacitor to stabilize the charge pump.
Rev. 1.0
35