C8051F960-B-GM Datasheet, PDF (212/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
15.5. Encoding/Decoding with SFR Access
The steps to perform a Encode/Decode operation using SFR access with the ENC0 module are as follow:
1. Clear ENC0CN by writing 0x00.
2. Write the input data to ENC0H:M:L.
3. Write the operation value to ENC0CN setting ENC, DEC, and MODE bits as desired and clearing all
other bits.
a. Write 0x10 for Manchester Decode operation.
b. Write 0x11 for Three-out-of-Six Decode operation.
c. Write 0x20 for Manchester Encode operation.
d. Write 0x21 for Three-out-of-Six Encode operation.
4. Wait on the READY bit in ENC0CN.
5. For a decode operation only, check the ERROR bit in ENC0CN for a decode error.
6. Read the results from ENC0H:M:L.
7. Repeat steps 2-6 for all remaining data.
Note that all of the ENC0 SFRs are on SFR page 0x2. The READY and ERROR must be cleared in
ENC0CN with each operation.
15.6. Decoder Error Interrupt
The Encoder/Decoder peripheral is capable of generating an interrupt on a decoder error. Normally, when
used with the DMA, the DMA will transfer the entire specified transfer size to and from the
Encoder/Decoder peripheral. If a decoder error occurs, decoding will continue until all data has been
decoded. The error bit in the ENC0CN SFR will indicate if an error has occurred anywhere in the DMA
transfer. Some applications will discard the entire packet after a single decoder error. Aborting the decoder
operation at the first decoder error will conserve energy and minimize packet receiver turn-around time.
The decoder interrupt service routine should first stall the ENC0 DMA channels by selecting the ENC0
DMA channels and then setting the STALL bit. Then disable the DMA channels by clearing the relevant
DMA0EN bits. In addition, clear any ENC DMA channel interrupts by clearing the respective bits in
DMA0NINT.
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