C8051F960-B-GM Datasheet, PDF (433/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
To initiate a Master mode Bidirectional data transfer:
1. Configure the SPI1 SFRs normally for Master mode.
a. Enable Master mode by setting bit 6 in SPI1CFG.
b. Configure the clock polarity CKPOL and clock phase CKPHA as desired in SPI1CFG.
c. Configure SPI1CKR for the desired SPI clock rate.
d. Configure the desired 4-wire master or 3-wire master mode in SPI1CN.
e. Enable the SPI by setting bit 0 of SPI1CN.
2. Configure the first DMA channel for the XRAM-to-SPI1DATA transfer:
a. Disable the first DMA channel by clearing the corresponding bit in DMA0EN.
b. Select the first DMA channel by writing to DMA0SEL.
c. Configure the selected DMA channel to use the XRAM-to-SPI1DAT peripheral request by writing
0x03 to DMA0NCF.
d. Write 0 to DMA0NMD to disable wrapping.
e. Write the address of the first byte of master output (MOSI) data to DMA0NBAH:L.
f. Write the size of the SPI transfer in bytes to DMA0NSZH:L.
g. Clear the address offset SFRs CMA0A0H:L.
3. Configure the second DMA channel for the SPI1DAT-to-XRAM transfer:
a. Disable the second DMA channel by clearing the corresponding bit in DMA0EN.
b. Select the second DMA channel by writing to DMA0SEL.
c. Configure the selected DMA channel to use the SPI1DAT-to-XRAM peripheral request by writing
0x04 to DMA0NCF.
d. Enable DMA interrupts for the second channel by setting bit 7 of DMA0NCF.
e. Write 0 to DMA0NMD to disable wrapping.
f. Write the address for the first byte of master input (MISO) data to DMA0NBAH:L.
g. Write the size of the SPI transfer in bytes to DMA0NSZH:L.
h. Clear the address offset SFRs CMA0A0H:L.
i. Enable the interrupt on the second channel by setting the corresponding bit in DMA0INT.
j. Enable DMA interrupts by setting bit 5 of EIE2.
4. Clear the interrupt bits in DMA0INT for both channels.
5. Enable both channels by setting the corresponding bits in the DMA0EN SFR to initiate the SPI
transfer operation.
6. Wait on the DMA interrupt.
7. Clear the DMA enables in the DMA0EN SFR.
8. Clear the DMA interrupts in the DMA0INT SFR.
Rev. 1.0
433