C8051F960-B-GM Datasheet, PDF (230/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
Table 16.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
PMU0MD
0xB3
0x0 _{Power Management Unit Mode}
PSBANK
0x84 All Pages Flash Page Switch Bank SFR
PSCTL
0x8F All Pages _{Program Store R/W Control}
PSW
0xD0 All Pages _{Program Status Word}
REF0CN
0xD1
0x0 Voltage Reference Control
REG0CN
0xC9
0x0 _{Voltage Regulator (REG0) Control}
REVID
0xEA
0xF _{Revision ID}
RSTSRC
0xEF
0x0 Reset Source Configuration/Status
RTC0ADR
0xAC
0x0 _{RTC0 Address}
RTC0DAT
0xAD
0x0 _{RTC0 Data}
RTC0KEY
0xAE
0x0 RTC0 Key
SBUF0
0x99
0x0 _{UART0 Data Buffer}
SCON0
0x98 All Pages _{UART0 Control}
SFRLAST
0x86 All Pages SFR Page Stack Last
SFRNEXT
0x85 All Pages _{SFR Page Stack Next}
SFRPAGE
0xA7 All Pages _{SFR Page}
SFRPGCN
0x8E
0xF SFR Page Control
SMB0ADM
0xF5
0x0 _{SMBus Slave Address Mask}
SMB0ADR
0xF4
0x0 _{SMBus Slave Address}
SMB0CF
0xC1
0x0 SMBus0 Configuration
SMB0CN
0xC0 All Pages _{SMBus0 Control}
SMB0DAT
0xC2
0x0 SMBus0 Data
SPI0CFG
0xA1
0x0 _{SPI0 Configuration}
SPI0CKR
0xA2
0x0 _{SPI0 Clock Rate Control}
SPI0CN
0xF8
0x0 SPI0 Control
SPI0DAT
0xA3
0x0 _{SPI0 Data}
SPI1CFG
0xA1
0x2 _{SPI1 Configuration}
SPI1CKR
0xA2
0x2 SPI1 Clock Rate Control
SPI1CN
0xF8
0x2 _{SPI1 Control}
SPI1DAT
0xA3
0x2 _{SPI1 Data}
SP
0x81 All Pages Stack Pointer
TCON
0x88 All Pages _{Timer/Counter Control}
TH0
0x8C
0x0 _{Timer/Counter 0 High}
TH1
0x8D
0x0 Timer/Counter 1 High
230
Rev. 1.0
Page
267
127
253
123
102
277
249
285
298
299
298
408
407
221
220
219
218
392
391
387
389
393
418
420
419
420
438
440
439
440
122
450
453
453