C8051F960-B-GM Datasheet, PDF(15/492 Page) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

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C8051F960-B-GM Datasheet, PDF (15/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

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C8051F96x

Table 15.5. Three-out-of-Six Decoding ................................................................. 211

Table 16.1. SFR Map (0xC0â0xFF) ...................................................................... 222

Table 16.2. SFR Map (0x80â0xBF) ....................................................................... 223

Table 16.3. Special Function Registers ................................................................. 224

Table 17.1. Interrupt Summary .............................................................................. 234

Table 18.1. Flash Security Summary .................................................................... 248

Table 19.1. Power Modes ...................................................................................... 257

Table 20.1. IPeak Inductor Current Limit Settings ................................................. 270

Table 23.1. Recommended XFCN Settings for Crystal Mode ............................... 288

Table 23.2. Recommended XFCN Settings for RC and C modes ......................... 289

Table 24.1. SmaRTClock Internal Registers ......................................................... 296

Table 24.2. SmaRTClock Load Capacitance Settings .......................................... 302

Table 24.3. SmaRTClock Bias Settings ................................................................ 303

Table 25.1. Pull-Up Resistor Current ..................................................................... 315

Table 25.2. Sample Rate Duty-Cycle Multiplier ..................................................... 315

Table 25.3. Pull-Up Duty-Cycle Multiplier .............................................................. 315

Table 25.4. Average Pull-Up Current (Sample Rate = 250 Âµs) ............................. 316

Table 25.5. Average Pull-Up Current (Sample Rate = 500 Âµs) ............................. 316

Table 25.6. Average Pull-Up Current (Sample Rate = 1 ms) ............................... 316

Table 25.7. Average Pull-Up Current (Sample Rate = 2 ms) ................................ 316

Table 26.1. Bit Configurations to select Contrast Control Modes .......................... 338

Table 27.1. Port I/O Assignment for Analog Functions ......................................... 353

Table 27.2. Port I/O Assignment for Digital Functions ........................................... 354

Table 27.3. Port I/O Assignment for External Digital Event Capture Functions .... 354

Table 28.1. SMBus Clock Source Selection .......................................................... 385

Table 28.2. Minimum SDA Setup and Hold Times ................................................ 386

Table 28.3. Sources for Hardware Changes to SMB0CN ..................................... 390

Table 28.4. Hardware Address Recognition Examples (EHACK = 1) ................... 391

Table 28.5. SMBus Status Decoding With Hardware ACK Generation Disabled

(EHACK = 0) ....................................................................................... 398

Table 28.6. SMBus Status Decoding With Hardware ACK Generation Enabled

(EHACK = 1) ....................................................................................... 400

Table 29.1. Timer Settings for Standard Baud Rates ï

Using The Internal 24.5 MHz Oscillator .............................................. 409

Table 29.2. Timer Settings for Standard Baud Rates ï

Using an External 22.1184 MHz Oscillator ......................................... 409

Table 30.1. SPI Slave Timing Parameters ............................................................ 423

Table 31.1. SPI Slave Timing Parameters ............................................................ 443

Table 32.1. Timer 0 Running Modes ..................................................................... 446

Table 33.1. PCA Timebase Input Options ............................................................. 467

Table 33.2. PCA0CPM and PCA0PWM Bit Settings for PCA ï

Capture/Compare Modules ................................................................ 469

Table 33.3. Watchdog Timer Timeout Intervals1 ................................................... 479

Rev. 1.0

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