C8051F960-B-GM Datasheet, PDF (355/492 Pages) Silicon Laboratories – Ultra Low Power 128K, LCD MCU Family

C8051F96x
27.3. Priority Crossbar Decoder
The Priority Crossbar Decoder assigns a Port I/O pin to each software selected digital function using the
fixed peripheral priority order shown in Figure 27.3. The registers XBR0, XBR1, and XBR2 defined in SFR
Definition 27.1, SFR Definition 27.2, and SFR Definition 27.3 are used to select digital functions in the
Crossbar. The Port pins available for assignment by the Crossbar include all Port pins (P0.0–P2.6) which
have their corresponding bit in PnSKIP set to 0.
From Figure 27.3, the highest priority peripheral is UART0. If UART0 is selected in the Crossbar (using the
XBRn registers), then P0.4 and P0.5 will be assigned to UART0. The next highest priority peripheral is
SPI1. If SPI1 is selected in the Crossbar, then P2.0–P2.2 will be assigned to SPI1. P2.3 will be assigned if
SPI1 is configured for 4-wire mode. The user should ensure that the pins to be assigned by the Crossbar
have their PnSKIP bits set to 0.
For all remaining digital functions selected in the Crossbar, starting at the top of Figure 27.3 going down,
the least-significant unskipped, unassigned Port pin(s) are assigned to that function. If a Port pin is already
assigned (e.g., UART0 or SPI1 pins), or if its PnSKIP bit is set to 1, then the Crossbar will skip over the pin
and find next available unskipped, unassigned Port pin. All Port pins used for analog functions, GPIO, or
dedicated digital functions such as the EMIF should have their PnSKIP bit set to 1.
Figure 27.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP =
0x00); Figure 27.4 shows the Crossbar Decoder priority with the External Oscillator pins (XTAL1 and
XTAL2) skipped (P0SKIP = 0x0C).
Important Notes:
 The Crossbar must be enabled (XBARE = 1) before any Port pin is used as a digital output. Port output
drivers are disabled while the Crossbar is disabled.
 When SMBus is selected in the Crossbar, the pins associated with SDA and SCL will automatically be
forced into open-drain output mode regardless of the PnMDOUT setting.
 SPI0 can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-
NSSMD0 bits in register SPI0CN. The NSS signal is only routed to a Port pin when 4-wire mode is
selected. When SPI0 is selected in the Crossbar, the SPI0 mode (3-wire or 4-wire) will affect the pinout
of all digital functions lower in priority than SPI0.
 For given XBRn, PnSKIP, and SPInCN register settings, one can determine the I/O pin-out of the
device using Figure 27.3 and Figure 27.4.
Rev. 1.0
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